The company said it will continue support for its current Z8 Encore! The devices are designed to meet the needs of designers working on consumer and. Microcontroller (MCU) Develop- because our kit then serves as your complete Z8 Encore!® additional cost allowing you to begin your design immedi- ately. What would be better than designing a softcore to learn more about VHDL ( VHSIC hardware I ended up choosing a modern Z relative: the Zilog Z8 Encore!.
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This article is focused on learning how a microcontroller core is designed, and is intended for educational use only. I began by learning the basics while exploring the classic Zilog Z Figure 1a. Fast forward through a career of programming that included authoring some books on microcontroller programming see Resourcesstarting a small design house ScTecand finishing a post-graduation program at CEFET-SC another Brazilian university located in Florianopolis.
This was inwhen I had more contact with programmable logic and VHDL and my curiosity was peaked. I ended up choosing a modern Z relative: With its lightweight IDE integrated development environment and free ANSI C compiler, it is an excellent project to learn and also teach about embedded systems.
The eZ8 core also includes a vectored interrupt controller with programmable priority and an on-chip debugger which communicates with the host computer using asynchronous serial communication. These microcontrollers are packed with a very nice peripheral set, ranging from versatile bit timers to motor control timers, from multiple UARTs IrDA ready to USB devices, and much more visit www.
One major feature of the eZ8 programming model is the lack of a fixed accumulator. Instead, any of the 4, possible RAM addresses can work as accumulators. In order to accomplish that, RAM is split into register groups there are groups of 16 working registers each. An instruction usually works within a single working register group, which is selected by an SFR named RP register pointer. Regarding the instruction set, there are 83 different instructions split into two opcode pages.
It comprises usual instructions for basic operations such as addition, subtraction, logical operations, data manipulation instructions, shifting instructions, change-of-flow instructions, some bit instructions, bit testing and manipulation, 8×8 multiply, etc. The program memory area is organized so that the first addresses are dedicated to special purposes. Addresses 0x and 0x are dedicated to the configuration options; addresses 0x and 0x store the reset vector; and so on.
Table 1 shows program memory organization. The first implementation of FPz8 uses a very conservative and hardwired design approach with two main buses: FPz8 includes 16, bytes of program memory implemented using synchronous block RAM which means program memory content is lost when the device is powered down. The five register area buses comprise three for the file register area user RAMand another two dedicated to special function registers.
Figure 2 shows a block diagram of the FPz8; you can see the CPU, two memory units one for program storage and the other for data storageand also an external timer module. Note that I am not using bidirectional buses for any interconnects in this project.
Unidirectional buses are simpler to use, although they are less space efficient. The VHDL description of the FPz8 is large and a bit complex, so I am going to split its operation into some modules to ease comprehension:. Fetching instructions is a primary task for any CPU. That means the CPU can fetch a new instruction while another is reading or writing into data memory.
Building Your Own Microcontroller | Nuts & Volts Magazine
The eZ8 has a variable length instruction word instruction length varies from one byte up to five bytes ; some instructions are lengthy but run faster than others. So, how can we successfully decode all these instructions? With an instruction queue; that is, a mechanism that keeps fetching bytes from program memory and storing them into an eight-byte array:.
There is also a structure IQUEUE which stores several internal parameters fetching state, read and write pointers, queue array itself, a counter, and a full indicator. The queue counter CNT is used to identify the number of bytes available for use reading in the queue. The decoder stage uses this number to verify that the desired number of bytes for the instruction is already available in the queue. This is where the actual magic happens.
The instruction decoder reads opcodes from the instruction queue and translates them into corresponding operations. Instruction decoder design started by figuring out the relation among all the instructions and addressing modes. Decoding an INC r1 instruction is simple: If we look at row 0x1, we can see that columns 0x0 and 0x1 are RLC instructions, and columns 0x2 up to 0x9 are ADC instructions.
So, we can design an ALU which takes a nibble as input the higher nibble from the opcode and decodes it accordingly. While this would work for columns 0x2 to 0x9, we would need another approach for the first two columns.
That is why I ended up writing two units: Another important detail is that all instructions within the same column and group are the same size in bytes, thus can be decoded in the same decoder section. The decoder design makes use of a large finite state machine FSM which advances on each clock tick. This is where the decoder actually decodes the opcodes, prepares buses and internal supporting signals, and steps to other execution states.
Among all those states, two are widely used by a lot of instructions: Can you guess why? Refer to Figure 4.
Building Your Own Microcontroller
In the beginning, some temporary variables are initialized to a default condition. Its value is used in the last part of this stage to increment the PC program counter mirocontroller, advance the queue read pointer, and decrement the number of available bytes in the queue. Following the initialization section, we can see the interrupt processing section. It is responsible for detecting any pending interrupts and prepares the CPU accordingly.
The actual instruction decoding block checks whether a low power mode is not active and also if 8z debugger mode is off OCDCR. It then checks the available bytes in the queue and proceeds with decoding. Note that some instruction decoding can make use of several functions and procedures written specially for the FPz As I said before, eZ8 has a vectored interrupt controller with programmable priority.
At first, I thought this section would not be so difficult because interrupts are no big deal, right?
Well, when I started to figure out how to do all the needed tasks saving context, vectoring, managing priorities, etc. After a couple hours, I came up with the current design. The design makes use of a nested IF chain micrcontroller generates a vector address upon detection of an interrupt event regarding an enabled interrupt.
Figure 5 shows a compressed view of the interrupt system. This is a simple counter used by the ATM instruction it disables interrupts for three instruction cycles, allowing atomic operations. One last comment regarding interrupts: The interrupt flag register IRQ0 samples interrupt inputs every rising edge of the system clock.
My OCD design implements almost all commands available on the real hardware, except for those related to data memory debug commands 0x0C and 0x0D ; the read runtime counter 0x3 ; and the read program memory CRC 0x0E. One thing I would like to highlight is care is needed when dealing with asynchronous signals inside FPGAs.
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The result was absolutely weird. My design had worked flawlessly in simulation. To my surprise, while most of the time I could successfully send commands and receive the expected results, sometimes the design would simply freeze and stop responding. A soft reset would make things go back to their proper operation, but that was intriguing me. After a lot of tests and some Googling, I figured out that it was microcontdoller related to the asynchronous edges of the serial input signal.
I then included a cascaded latch to synchronize the signal to my internal clock and all the problems were gone! That is a tough way to learn that you must always synchronize external signals prior to feeding them into complex logic! I must say that debugging and refining the debugger code was the hardest part of this project; mostly because it interacts with all the other subsystems including buses, the decoder, and instruction queue.
Once fully compiled I used Quartus II v9. While this is a lot, there are still some 1, logic elements available for peripherals my simple bit timer adds up to around logic elements and 61 registers.
The mini board features along with the EP4CE6 device: After thinking a bit and reading compiler output messages, I figured out that it was probably a timing issue. Checking the timing analysis messages, I could see a warning that the maximum clock should be around 24 MHz.
I then used a divider-by Everything started to work perfectly! Using the FPz8 is very simple and straightforward. You can supply a hex file and use the MegaWizard Plug-in Manager to change the program memory initialization file. That way, your application code will start running following a reset signal.
Before connecting, make sure that debugger settings are the same as in Figure 8. You can set the desired communication speed as well;bps works very well for me. Just ignore the warning and proceed with the debugging session.
Once the code is successfully downloaded, you can start the application GO buttonstep instructions, inspect or edit registers, set breakpoints, etc. Just keep in mind that the FPz8 has a volatile program memory.
Thus, any program downloaded to it is lost when the FPGA is powered down. This project took me a couple weeks to complete, but it was delightful to research and design a microcontroller core. Need to brush up on your electronics principles? These multi-part series may be just what you need! Simplified program memory organization. Learning Electronics Need to brush up on your electronics principles?