DSE. Pin TSSOP. DSEN Pin TSSOP (Industrial). PIN ASSIGNMENT. DS Serial Alarm Real Time Clock (RTC) VCC2. 1. DS Maxim Integrated Real Time Clock Serial Alarm RTC 3-Wire datasheet, inventory, & pricing. Maxim Integrated DS+: available from 18 distributors. Explore Integrated Circuits (ICs) on Octopart: the fastest source for datasheets, pricing, specs.
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The end of dss1305 month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The DS will maintain the time and date, provided the oscillator is enabled, as long as at least one supply is at a valid level. This allows an easy interface to 3V logic in mixed supply systems.
The DS offers dual-power supplies as well as a battery input pin. The dual power supplies support a programmable trickle charge circuit that allows a rechargeable energy source such as a super cap or rechargeable battery to be used for dayasheet backup supply.
The VBAT pin allows the device to be backed up by a non-rechargeable battery. The DS is fully operational from 2. Two programmable time-of-day alarms are provided by the DS Each alarm can generate an interrupt on a programmable combination of seconds, minutes, hours, and day.
The time-ofday alarms can be programmed to assert two different interrupt outputs or to assert one common interrupt output. A straightforward address and data format is implemented in which data transfers can occur 1 byte at a time or in multiple-byte-burst mode.
This is the secondary power supply pin. In systems using the trickle charger, the rechargeable energy source is connected to this pin. If not used, VBAT must be connect to ground.
Diodes must not be placed in series between VBAT and the battery, or improper operation will result. UL recognized to ensure against reverse charging current when used in conjunction with a lithium battery.
Connections for Standard The internal oscillator is designed for operation with a crystal having a specified load capacitance of 6pF. For more information on crystal selection and crystal layout considerations, refer to Application Note The DS can also be driven by an external In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. The INT0 pin is an active-low output of the DS that can be used as an interrupt input to a processor.
The INT0 pin can be programmed to be asserted by only Alarm 0 or can be programmed to be asserted by either Alarm 0 or Alarm 1.
The INT0 pin remains low as long as the status bit causing the interrupt is present and the corresponding interrupt enable bit is set. The INT0 pin is an open-drain output and requires an external pullup resistor. Active-Low Interrupt 1 Output. The INT1 pin is an active-low output of the DS that can be used as an interrupt input to a processor.
The INT1 pin can be programmed to be asserted by Alarm 1 only. The INT1 pin remains low as long as the status bit causing the interrupt is present and the corresponding interrupt enable bit is set. The INT1 pin is an open-drain output and requires an external pullup resistor.
The two interrupts and the internal clock continue to run regardless of the level of VCC as long as a power source is present. Ground Serial Interface Mode. When connected to GND, standard 3-wire communication is selected. The chip-enable signal must be asserted high during a read or a write for both 3-wire and SPI communication. This pin has an internal 55k? Interface Logic Power-Supply Input. This pin is physically connected to the source connection of the p-channel transistors in the output buffers of the SDO and PF pins.
DC power is provided to the device on this pin.
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The following paragraphs describe the function of each pin. Additional error is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit can result in the clock running fast. The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Applications Note The time, calendar, and alarm are set or initialized by writing the appropriate register bytes. Note that some bits are set to 0.
These bits always read 0 regardless of how they are written. Also note that registers 12h to 1Fh read and registers 92h to 9Fh are reserved. These registers always read 0 regardless of how they are written. The contents of the time, calendar, and alarm registers are in the BCD format. The day register increments at midnight.
Values that correspond to the day of week are user-defined but must be sequential e. Illogical time and date entries result in undefined operation. Except where otherwise noted, the initial power on state of all registers is not defined.
However, the countdown chain is reset when the seconds register is written. Writing the time and date registers within one second after writing the seconds register ensures consistent data. Terminating a write before the last bit is sent aborts the write for that byte. When reading in burst mode, the user copy is static while the internal registers continue to increment. The DS can be run in either hour or hour mode. Bit 6 of the hours register is defined as the or hour mode select bit.
When high, the hour mode is selected. In the hour mode, bit 5 is the second hour bit 20 to 23 hours. The DS contains two time-of-day alarms.
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Time-of-day Alarm 0 can be set by writing to registers 87h to 8Ah. Time-of-day Alarm 1 can be set by writing to registers 8Bh to 8Eh. The alarms can be programmed by the INTCN bit of the control register to operate in two different modes; each alarm can drive its own separate interrupt output or both alarms can drive a ds1035 interrupt output.
Bit 7 of each of the time-of-day alarm registers are mask bits Table 2. When all of the mask bits are logic 0, a timeof-day alarm only occurs once per week when the values stored in timekeeping registers 00h to 03h match the values stored in the time-of-day alarm registers. An alarm is generated every day when bit 7 of the day alarm register is set to a logic datashet.
An alarm is generated every hour when bit 7 of dataeheet day and hour alarm registers is set to a logic 1. Similarly, an alarm is generated every minute when bit 7 of the day, 6 of 22 http: When bit 7 of the day, hour, ds11305, and seconds alarm registers is set to a logic datasheeg, alarm occurs every second.
During each clock update, the RTC compares the Alarm 0 and Alarm 1 registers with the corresponding clock registers. When a match occurs, the corresponding alarm flag bit in the status register is set to a 1. If the corresponding alarm interrupt enable bit is enabled, an interrupt output is activated. When this bit is set to a logic 1, the oscillator is stopped and the DS is placed into a low-power standby mode with a current drain of less than nA when power is supplied by VBAT or VCC2.
Ds3105 initial application of power, this bit will be set to a logic 1. When high, the write protect bit prevents a write operation to any register, including bits 0, 1, 2, and 7 of the control datashete.
Upon initial power-up, the state of the WP bit is undefined. Therefore, the WP bit should be cleared before attempting to write to the device. When the INTCN bit is set vs1305 a logic 1, a match between the timekeeping registers and the Alarm 0 registers activates the INT0 pin provided that the alarm is enabled and a match between the timekeeping registers and the Alarm 1 registers activate the INT1 pin provided that the alarm is enabled. IRQF0 is cleared when the address pointer goes datsheet any of the Alarm 0 registers during a read or write.
IRQF1 is cleared when the address pointer goes to any of the Alarm 1 registers during a read or write.
The simplified daatasheet of Figure 3 shows the basic components of the trickle charger. The trickle-charge select TCS bits bits 4—7 control the selection of the trickle charger. To prevent datqsheet enabling, only a pattern of enables the datsaheet charger. All other patterns disable the trickle charger.
On the initial application of power, the DS powers up with the trickle charger disabled. Initial power-on state The user determines diode and resistor selection according to the maximum current desired for battery or super cap charging.
The maximum charging current can be calculated as illustrated in the following example. The maximum current IMAX would, therefore, be calculated as follows: Three different power-supply configurations are illustrated in Figure 4.
Configuration 1 shows the DS being backed up by a nonrechargeable energy source such as a lithium battery. Configuration 2 illustrates the DS being backed up by a rechargeable energy source. The DS does not write-protect itself in this configuration. Configuration 3 shows the DS in battery operate mode datasheeet the device is powered only by a single battery.
Only these three configurations are allowed. Unused supply pins must be grounded.